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Tri path Technol og y, I nc. - Techni cal I nformation
TA2024C STEREO 15W (4) CLASS-TTM DIGITAL AUDIO AMPLIFIER USING DIGITAL POWER PROCESSINGTM TECHNOLOGY
Preliminary Information Revision 1.0 - January 2006
GENERAL DESCRIPTION
The TA2024C is a 15W/ch continuous average two-channel Class-T Digital Audio Power Amplifier IC using Tripath's proprietary Digital Power ProcessingTM technology. Class-T amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers. The TA2024C has incorporated specific changes to improve the click and pop performance over previous devices such as TA2024 and TA2024B. The TA2024C is recommended for all new designs that previously used the TA2024 or TA2024B.
APPLICATIONS FEATURES
Computer/PC Multimedia DVD Players Cable Set-Top Products Televisions Video CD Players Battery Powered Systems
BENEFITS
Fully integrated solution with FETs Easier to design-in than Class-D Reduced system cost with no heat sink Dramatically improves efficiency versus ClassAB Signal fidelity equal to high quality linear amplifiers High dynamic range compatible with digital media such as CD, DVD, and Internet audio
TYPICAL PERFORMANCE
Class-T architecture Single Supply Operation "Audiophile" Quality Sound 0.03% THD+N @ 9W, 4 0.10% IHF-IM @ 1W, 4 11W @ 4, 0.1% THD+N 6W @ 8, 0.1% THD+N High Power 15W @ 4, 10% THD+N 10W @ 8, 10% THD+N High Efficiency 81% @ 15W, 4 90% @ 10W, 8 Dynamic Range = 98 dB Mute and Sleep inputs Enhanced Turn-on & turn-off pop suppression Over-current protection Over-temperature protection Bridged outputs 36-pin Power SOP package
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A B S O L U T E M A X I M U M R A T I N G S (Note 1)
SYMBOL VDD V5 SLEEP MUTE TSTORE TA TJ Supply Voltage Input Section Supply Voltage SLEEP Input Voltage MUTE Input Voltage Storage Temperature Range Operating Free-air Temperature Range Junction Temperature PARAMETER Value 16 6.0 -0.3 to 6.0 -0.3 to V5+0.3 -40 to 150 0 to 70 150 UNITS V V V V C C C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: See Power Dissipation Derating in the Applications Information section.
O P E R A T I N G C O N D I T I O N S (Note 4)
SYMBOL VDD VIH VIL Supply Voltage High-level Input Voltage (MUTE, SLEEP) Low-level Input Voltage (MUTE, SLEEP) PARAMETER MIN. 8.5 3.5 1 TYP. 12 MAX. 14.0 UNITS V V V
Note 3: Recommended Operating Conditions indicate conditions for which the device is functional. See Electrical Characteristics for guaranteed specific performance limits.
THERMAL CHARACTERISTICS
SYMBOL JC JA PARAMETER Junction-to-case Thermal Resistance Junction-to-ambient Thermal Resistance (still air) VALUE UNITS 2.5 50 C/W C/W
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ELECTRICAL CHARACTERISTICS
See Test/Application Circuit. Unless otherwise specified, VDD = 12V, f = 1kHz, Measurement Bandwidth = 22kHz, RL = 4, TA = 25 C, Package heat slug soldered to 2.8 square-inch PC pad.
SYMBOL PO PARAMETER Output Power (Continuous Average/Channel) CONDITIONS THD+N = 0.1% THD+N = 10% IDD,MUTE IDD, SLEEP Iq THD + N IHF-IM SNR CS PSRR VOFFSET VOH VOL eOUT Mute Supply Current Sleep Supply Current Quiescent Current Total Harmonic Distortion Plus Noise IHF Intermodulation Distortion Signal-to-Noise Ratio Channel Separation Power Supply Rejection Ratio Power Efficiency Output Offset Voltage High-level output voltage (FAULT & OVERLOAD) Low-level output voltage (FAULT & OVERLOAD) Output Noise Voltage MUTE = VIH SLEEP = VIH VIN = 0 V PO = 9W/Channel 19kHz, 20kHz, 1:1 (IHF) A-Weighted, POUT = 15W, RL = 4 f = 1 kHz 20 Hz < f < 20 kHz VDD = 9V to 13.2V Vripple = 100mVrms, f=1kHz POUT = 10W/Channel, RL = 8 No Load, MUTE = Logic Low 3.5 1 A-Weighted, input AC grounded 100 50 65 RL = 4 RL = 8 RL = 4 RL = 8 MIN. 9 5.5 12 8 TYP. 11 6 15 10 25 0.25 61 0.03 0.10 98 85 60 75 65 90 50 150 0.5 TBD 2 75 MAX. UNITS W W W W mA mA mA % % dB dB dB dB dB % mV V V V
Note: Minimum and maximum limits are guaranteed but may not be 100% tested.
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PIN DESCRIPTION
Pin 2, 3 Function DCAP2, DCAP1 Description Charge pump switching pins. DCAP1 (pin 3) is a free running 300kHz square wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted 10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal), frequency, and phase as DCAP1. Digital 5VDC, Analog 5VDC Analog Ground Internal reference voltage; approximately 1.0 VDC. A logic low output indicates the input signal has overloaded the amplifier. Input stage output pins. Single-ended inputs. Inputs are a "virtual" ground of an inverting opamp with approximately 2.4VDC bias. When set to logic high, both amplifiers are muted and in idle mode. When low (grounded), both amplifiers are fully operational. If left floating, the device stays in the mute mode. This pin should be tied to GND if not used. Unlike previous Tripath devices, the input bias is still active, even if the MUTE pin is tied to a logic high. Input stage bias voltage (approximately 2.4VDC). When set to logic high, device goes into low power mode. If not used, this pin should be grounded A logic high output indicates thermal overload, or an output is shorted to ground, or another output. Power Grounds (high current) Digital Ground. Connect to AGND locally (near the TA2024C). Bridged output pairs Supply pins for high current H-bridges, nominally 12VDC. Not connected. Not bonded internally. Analog 12VDC Charge pump output (nominally 10V above VDDA) Regulated 5VDC source used to supply power to the input section (pins 4 and 9).
4, 9 5, 8, 17 6 7 10, 14 11, 15 12
V5D, V5A AGND1, AGND2, AGND3 REF OVERLOADB OAOUT1, OAOUT2 INV1, INV2 MUTE
16 18 19 20, 35 22 24, 27; 31, 28 25, 26, 29, 30 13, 21, 23, 32, 34 33 36 1
BIASCAP SLEEP FAULT PGND2, PGND1 DGND OUTP2 & OUTM2; OUTP1 & OUTM1 VDD2, VDD2 VDD1, VDD1 NC VDDA CPUMP 5VGEN
TA2024C PINOUT
36-pin Power SOP Package (Top View)
+5VGEN DCAP2 DCAP1 V5D AGND1 REF OVERLOADB AGND2 V5A OAOUT1 INV1 MUTE NC OAOUT2 INV2 BIASCAP AGND3 SLEEP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 CPUMP PGND1 NC VDDA NC OUTP1 VDD1 VDD1 OUTM1 OUTM2 VDD2 VDD2 OUTP2 NC DGND NC PGND2 FAULT
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APPLICATION /TEST CIRCUIT
TA2024C
CI 2.2uF +
OAOUT1 10 RF 20K INV1 11
VDD1 Lo 10uH, 2A
31 OUTP1
DO
RI 20K CA 0.1uF (Pin 8) 5V
BIASCAP
16
5V
Processing & Modulation
PGND1 VDD1
(Pin 35) (Pin 35) Lo 10uH, 2A
*Co 0.47uF
CZ 0.22uF CDO 0.01uF RL 4 or *8
28 OUTM1
DO (Pin 35)
*Co 0.47uF
RZ 10, 1/2W
MUTE
12
PGND1
19
OAOUT2 14
7
VDD2
FAULT OVERLOADB
CI 2.2uF +
RF 20K RI 20K
INV2
15
24 OUTP2
DO
REF
Lo 10uH, 2A
6
(Pin 8) RREF 8.25K, 1%
Processing & Modulation
PGND2 VDD2
(Pin 20) (Pin 20) Lo 10uH, 2A
*Co 0.47uF
CZ 0.22uF CDO 0.01uF
3
+12V 1M CD 0.1uF
DCAP1
27
OUTM2 DO
RZ *Co 0.47uF 10, 1/2W
RL 4 or *8
2 18
DCAP2
PGND2
SLEEP CPUMP 36
(Pin 20)
0.1uF CS 0.1uF To Pin 1
4 5 9
CS 0.1uF
+
V5D AGND1 V5A AGND2 AGND3
5V
VDDA DGND +5VGEN VDD1 VDD1 PGND1
33 22 1 30 29 35 25 26 20
CP 1uF CS 0.1uF CS 0.1uF To Pins 4,9
8 17
CSW 0.1uF
CSW 180uF, 16V
+
VDD (+12V)
13 21 23 32 34
VDD2 NC VDD2 PGND2
CSW 0.1uF
+
CSW 180uF, 16V
Note: Analog and Digital/Power Grounds must be connected locally at the TA2024B Analog Ground Digital/Power Ground All Diodes Motorola MBRS130T3 * Use Co = 0.22F for 8 Ohm loads
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E X T E R N A L C O M P O N E N T S D E S C R I P T I O N (Refer to the Application/Test Circuit)
Components RI RF CI RREF CA CD CP
Description Inverting Input Resistance to provide AC gain in conjunction with RF. This input is biased at the BIASCAP voltage (approximately 2.4VDC). Feedback resistor to set AC gain in conjunction with RI; A V = 12(RF / RI ) . Please refer to the Amplifier Gain paragraph in the Application Information section. AC input coupling capacitor which, in conjunction with RI, forms a highpass filter at
fC = 1 (2RICI )
CS CSW
CZ RZ
DO
LO
Bias resistor. Locate close to pin 6 (REF) and ground at pin 8 (AGND2). BIASCAP decoupling capacitor. Should be located close to pin 16. Charge pump input capacitor. This capacitor should be connected directly between pins 2 (DCAP2) and 3 (DCAP1) and located physically close to the TA2024C. Charge pump output capacitor that enables efficient high side gate drive for the internal H-bridges. To maximize performance, this capacitor should be connected directly between pin 36 (CPUMP) and pin 33 (VDDA). Please observe the polarity shown in the Application/ Test Circuit. Supply decoupling for the low current power supply pins. For optimum performance, these components should be located close to the pin and returned to their respective ground as shown in the Application/Test Circuit. Supply decoupling for the high current, high frequency H-Bridge supply pins. These components must be located as close to the device as possible to minimize supply overshoot and maximize device reliability. Both the high frequency bypassing (0.1uF) and bulk capacitor (180uF) should have good high frequency performance including low ESR and low ESL. Panasonic HFQ or FC capacitors are ideal for the bulk capacitor. Zobel Capacitor. Zobel resistor, which in conjunction with CZ, terminates the output filter at high frequencies. The combination of RZ and CZ minimizes peaking of the output filter under both no load conditions or with real world loads, including loudspeakers which usually exhibit a rising impedance with frequency. Schottky diodes that minimize undershoots of the outputs with respect to power ground during switching transitions. For maximum effectiveness, these diodes must be located close to the output pins and returned to their respective PGND. Please see Application/Test Circuit for ground return pin. Output inductor, which in conjunction with CO and CDO, demodulates (filters) the switching waveform into an audio signal. Forms a second order filter with a cutoff frequency of f C = 1 ( 2 L O C TOT ) and a quality factor of
Q = R L C TOT
CO CDO
2 L O C TOT where CTOT = CO || 2 * CDO.
Output capacitor. Differential Output Capacitor. Differential noise decoupling for reduction of conducted emissions. Must be located near chassis exit point for maximum effectiveness.
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TYPICAL PERFORMANCE
Frequency Response
100 90 80 70
RL = 8 RL = 4
Efficiency versus Output Power
+3 +2.5 +2
VDD = 12V Pout = 1W CO and CZ = .22uF for 8
Output Amplitude (dBr)
+1.5 +1 +0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3 20 50 100 200 500 1k 2k 5k 10k 20k
RL = 4 R L = 8
Efficiency (%)
60 50 40 30 20 10 0 0 5 10 15 20
VDD = 12V f = 1kHz THD+N < 10%
Output Power (W)
Frequency (Hz)
Intermodulation Distortion
+0 -10 19kHz, 20kHz, 1:1 -20 Pout = 1W -30 RL = 4
32k FFT VDD = 12V
Noise Floor
+0 -10 -20 -30
VDD = 12V RL = 4 32k FFT FS = 65kHz Av = 12V/V BW = 22Hz - 20kHz(AES17)
Noise FFT (dBV)
-40 FS = 65kHz
FFT (dBr)
-50 BW = 22Hz - 80kHz -60 -70 -80 -90 -100 -110 -120 -130 20 50 100 200 500 1k 2k 5k 10k 20k 30k
f = 1kHz
-40 -50 -60 -70 -80 -90 -100 -110 -120
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
THD+N versus Frequency
1
VDD = 12V Po @ 4 = 4W Po @ 8 = 2W 0.2 BW = 22Hz - 22kHz C O and CZ = 0.22uF for 8
Frequency (W)
0.5
THD+N (%)
0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 50 100 200 500 1k
RL = 4 RL = 8
2k
5k
10k
20k
Frequency (Hz)
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TYPICAL PERFORMANCE
Channel Separation versus Frequency
+0
T T T T T T T T
Channel Separation versus Frequency
+0
T T T T T T T T
Channel Separation (dBr)
Channel Separation (dBr)
VDD = 12V -10 Po = 1W RL = 4 -20 BW = 22Hz - 22kHz L6, L7, L8, L9 = 8RHB2 Inductors
-30 -40 -50 -60
-10 VDD = 12V Po = 1W RL = 4 -20 BW = 22Hz - 22kHz L6, L7, L8, L9 = DS86 Inductors -30 -40 -50 -60 -70 -80 -90 -100 20 50 100 200 500 1k 2k 5k 10k 20k
-70 -80 -90 -100 20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz)
Frequency (Hz)
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APPLICATION INFORMATION Layout Recommendations
The TA2024C is a power (high current) amplifier that operates at relatively high switching frequencies. The outputs of the amplifier switch between the supply voltage and ground at high speeds while driving high currents. This high-frequency digital signal is passed through an LC low-pass filter to recover the amplified audio signal. Since the amplifier must drive the inductive LC output filter and speaker loads, the amplifier outputs can be pulled above the supply voltage and below ground by the energy in the output inductance. To avoid subjecting the TA2024C to potentially damaging voltage stress, it is critical to have a good printed circuit board layout. It is recommended that Tripath's layout and application circuit be used for all applications and only be deviated from after careful analysis of the effects of any changes. Please contact Tripath Technology for further information regarding reference design material regarding the TA2024C.
Output Stage layout Considerations and Component Selection Criteria
Proper PCB layout and component selection is a major step in designing a reliable TA2024C power amplifier. The supply pins require proper decoupling with correctly chosen components to achieve optimal reliability. The output pins need proper protection to keep the outputs from going below ground.
The above layout shows ideal component placement and routing for channel 1 (the same design criteria applies to channel 2). This shows that C3, a 0.1uF surface mount 0805 capacitor, should be the first component placed and must decouple VDD1 (pins 29 and 30) directly to PGND1 (pin35). C2, a low ESR, electrolytic capacitor, should also decouple VDD1 directly to PGND1. Both C2 and C3 may decouple VDD1 to a ground plane, but it is critical that the return path to the PGND1 pin of the TA2024C, whether it is a ground plane or a trace, be a short and direct low impedance path. Effectively decoupling VDD will shunt any power supply trace length inductance. The diodes and inductors shown are for channel 1's outputs. D1 and L2 connect to the OUTP1 pin and D2 and L3 connect to the OUTM1 pin of the TA2024C. Each output must have a Schottky or Ultra Fast Recovery diode placed near the TA2024C, preferably immediately after the decoupling capacitors and use short returns to PGND1. These low side diodes, D1 and D2, will prevent the outputs from going below ground. To be optimally effective they must have a short and direct return path to its proper ground pin (PGND1) of the TA2024C. This can be achieved with a ground plane or a trace. The output inductors, L2 and L3, should be placed close to the TA2024C without compromising the locations of the closely placed supply decoupling capacitors and output diodes. The purpose of placing the output inductors close to the TA2024C output pins is to reduce the trace length of the switching outputs. This will aid in reducing radiated emissions.
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Please see the External Component Description section on page 6 for more details on the abovementioned components. The Application/ Test Circuit refers to the low side diodes as DO, and both supply decoupling capacitors as CSW.
TA2024C Amplifier Gain
The ideal gain of the TA2024C is set by the ratio of two external resistors, RI and RF, and is given by the following formula:
VO R = - 12 F VI RI
where VI is the input signal level and VO is the differential output signal level across the speaker. Please note that VO is 180 out of phase with VI. The ideal gain of the TA2024C is 12V/V, whereas typical values are: AV = 11.5V/V for 4 and 11.7V/V for 8.
Mute Pin
The mute pin must be driven to a logic low or logic high state for proper operation. To enable the amplifier, connect the mute pin to a logic low. To enable the mute function, connect the mute pin to a logic high signal. Please note that the mute pin is a 5V CMOS input pin and the mute signal should be de-bounced to eliminate a possibility of falsely muting. When in mute, the internal processor bias voltages are still active in the TA2024C. This minimizes any turn on pop caused by charging the input coupling capacitor. It is recommended that the mute is held high during power up or power down to eliminate audible transients. If turn-on and/or turn-off noise is still present with a TA2024C amplifier, the cause may be other circuitry external to the TA2024C such as an audio processor or preamp. Multiple audio processors used in LCD TV's create audible pops as their power supply collapses. If the TA2024C is still active (mute pin is low), then these audible pops will be amplified and output to the speakers. To eliminate this problem, simply activate the mute before the power supply collapses.
Turn-on and Turn-off Noise
The TA20204C has improved mute-off and mute-on click performance as compared to previous Tripath devices including TA2024 and TA2024B. The main improvement was related to keeping the input stage biased up during mute, but other specific circuit details, beyond the scope of the data sheet, were also improved. But as with the previous devices, many complaints about turn on and off clicks were not actually caused by the TA2024C. As noted above, a typical cause of turn off pop is related to the audio processor that provides the audio input to the TA2024C amplifier. The audio processor used for most LCD TV's produces a pop when its power supply collapses. Thus, it is recommended that the TA2024C mute pin is pulled high before the power supply is removed. The time that it takes to activate mute has been reduced in the TA2024C as opposed to TA2024 and TA2024B. This allows for the mute to be activated before the audio processor power supply can collapse. Thus, any possibility of a pop being amplified by the TA2024C can be adverted. The remaining source of click is the residual output offset. This pop would normally be masked if the TA2024C is playing music but in some cases, may be undesirable due to application requirements. The level of the pop is proportional to the offset, which has a specified maximum of 150mV as stated in the Electrical Characteristics Section.
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In most cases, the pop caused by the output offset is not objectionable. But in those cases that there is concern about the residual pop, the offset can be nulled. There are several ways to trim the offset. These include using a trim pot, with current limiting resistor, using an active DC servo comprised of op-amps, resistors and switches, and finally, a look-up table of resistor values attached to the input. The last scheme is implemented on the EB-TA2024C. Please refer to the EB-TA2024C document at www.tripath.com for additional information on this circuit. Please note that while a DC servo is automatic, and thus, does not require manual adjustment, it is not the best solution. This is because the DC servo has to be slow enough so as not to react to low frequency audio signals. Thus, it is not possible for such a circuit to eliminate a mute off pop caused by DC offset. The servo is effective for eliminating mute on pops, since the DC offset would be nulled to zero by the time the TA2024C is muted. A DC servo, in conjunction, with a relay is an effective method for completely eliminating mute off and mute on pops, but due to the small residual pop caused by the TA2024C offset, it is unlikely that such a sophisticated scheme would be implemented for high-volume production designs.
Output Voltage Offset
The DC offset voltages that appear at the speaker terminals of a TA2024C amplifier are typically small and for most applications no DC offset correction is necessary. The TA2024C is 100% tested to ensure that the differential output DC offset voltage is less than +/-150mV. However this DC offset can cause a small turn on and turn off pop, depending on the offset value for that specific IC. Every TA2024C IC will have a different offset voltage for each channel. If the output offset is deemed unacceptable from a turn on/off pop standpoint, there are three recommended methods for correcting it. These methods of trimming the offset voltage are optional and for most cases the additional circuitry is not needed. 1) A potentiometer can be used at the input of the TA2024C as shown in the figure below. By changing the input bias voltage the output DC offset voltage can be trimmed. Two separate potentiometers must be used to trim both channels.
OAOUT1 29
CI 2.2uF +
RI 20K
RF 20K
INV1 30
ROFB 1M V5A (pin 28) ROFA 10K Offset Trim Potentiometer
TA2024C
COF 0.1uF
OAOUT2
1
CI 2.2uF +
RF RI 20K 20K
INV2
2
ROFB 1M V5A (pin 28) ROFA 10K Offset Trim Potentiometer
COF 0.1uF
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2) In cases where manually trimming potentiometers is not possible, resistors can be used in place of potentiometers. Since each TA2024C has different offset voltage, the output offset voltage will need to be measured for both channel 1 and channel 2 and then resistors will have to be added on the PC board to trim the offset. Below is a lookup table for resistor values for corresponding offset voltages. Both Rx and Ry values should be 1% tolerance resistors. Please refer to the EB-TA2024C document for more information on this manual trim method using resistors.
OAOUT1 29
CI 2.2uF +
RF RI 20K 20K
INV1 30
ROFB 1M V5A (pin 28) RX1 RY1
TAA2024C
OAOUT2
1
CI 2.2uF +
RI 20K
RF 20K
INV2
2
V5A (pin 28) RX2 RY2
ROFB 1M
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OFFSET
Ry
Rx (1%)
150mV 140mV 130mV 120mV 110mV 100mV 90mV 80mV 70mV 60mV 50mV 40mV 30mV 20mV 10mV 0mV -10mV -20mV -30mV -40mV -50mV -60mV -70mV -80mV -90mV -100mV -110mV -120mV -130mV -140mV -150mV
20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k
13.3k 13.7k 14.3k 14.7k 15.4k 15.8k 16.2k 16.9k 17.4k 17.8k 18.7k 19.1k 19.6k 20.5k 21k 21.5k 22.6k 23.2k 24.3k 24.9k 25.5k 26.7k 27.4k 28.0k 29.4k 30.1k 31.6k 32.4k 33.2k 34.8k 35.7k
3) A DC servo using a dual op amp can also be used to automatically null any offset voltage. This DC servo will only eliminate the turn off pop since the RC time constant of the DC servo is very slow. Please contact Tripath sales for additional information on the DC servo circuit.
Protection Circuits
The TA2024C is guarded against over-temperature and over-current conditions. When the device goes into an over-temperature or over-current state, the FAULT pin goes to a logic HIGH state indicating a fault condition. When this occurs, the amplifier is muted, all outputs are TRISTATED, and will float to 1/2 of VDD.
Over-temperature Protection
An over-temperature fault occurs if the junction temperature of the part exceeds approximately 155C. The thermal hysteresis of the part is approximately 45C, therefore the fault will automatically clear when the junction temperature drops below 110C.
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Over-current Protection
An over-current fault occurs if more than approximately 7 amps of current flows from any of the amplifier output pins. This can occur if the speaker wires are shorted together or if one side of the speaker is shorted to ground. An over-current fault sets an internal latch that can only be cleared if the MUTE pin is toggled or if the part is powered down. Alternately, if the MUTE pin is connected to the FAULT pin, the HIGH output of the FAULT pin will toggle the MUTE pin and automatically reset the fault condition.
Overload
The OVERLOADB pin is a 5V logic output. When low, it indicates that the level of the input signal has overloaded the amplifier resulting in increased distortion at the output. The OVERLOADB signal can be used to control a distortion indicator light or LED through a simple buffer circuit, as the OVERLOADB cannot drive an LED directly.
Sleep Pin
The SLEEP pin is a 5V logic input that when pulled high (>3.5V) puts the part into a low quiescent current mode. This pin is internally clamped by a zener diode to approximately 6V thus allowing the pin to be pulled up through a large valued resistor (1meg recommended) to VDD. To disable SLEEP mode, the sleep pin should be grounded.
Fault Pin
The FAULT pin is a 5V logic output that indicates various fault conditions within the device. These conditions include: low supply voltage, low charge pump voltage, low 5V regulator voltage, over current at any output, and junction temperature greater than approximately 155C. All faults except overcurrent all reset upon removal of the condition. The FAULT output is capable of directly driving an LED through a series 2k resistor. If the FAULT pin is connected directly to the MUTE input an automatic reset will occur in the event of an over-current condition.
Power Dissipation Derating
For operating at ambient temperatures above 25C the device must be derated based on a 150C maximum junction temperature, TJMAX as given by the following equation:
PDISS = (TJMAX - TA ) JA
where... PDISS = maximum power dissipation TJMAX = maximum junction temperature of TA2024C TA = operating ambient temperature JA = junction-to-ambient thermal resistance
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Where JA of the package is determined from the following graph:
JA vs Copper Area
50 C/W) 40 30 20 10 0 1 2 3 4 5 6 Copper Area (square inches) Pdiss - 1.35W Pdiss - 2W Pdiss - 3.4W
In the above graph, Copper Area is the size of the copper pad on the PC board to which the heat slug of the TA2024C is soldered. The heat slug must be soldered to the PC Board to increase the maximum power dissipation capability of the TA2024C package. Soldering will minimize the likelihood of an over-temperature fault occurring during continuous heavy load conditions. The vias used for connecting the heatslug to the copper area on the PCB should be 0.013" diameter.
Performance Measurements of the TA2024C
The TA2024C operates by generating a high frequency switching signal based on the audio input. This signal is sent through a low-pass filter (external to the Tripath amplifier) that recovers an amplified version of the audio input. The frequency of the switching pattern is spread spectrum and typically varies between 100kHz and 1.0MHz, which is well above the 20Hz - 20kHz audio band. The pattern itself does not alter or distort the audio input signal but it does introduce some inaudible components. The measurements of certain performance parameters, particularly noise related specifications such as THD+N, are significantly affected by the design of the low-pass filter used on the output as well as the bandwidth setting of the measurement instrument used. Unless the filter has a very sharp roll-off just beyond the audio band or the bandwidth of the measurement instrument is limited, some of the inaudible noise components introduced by the Tripath amplifiers switching pattern will degrade the measurement. One feature of the TA2024C is that it does not require large multi-pole filters to achieve excellent performance in listening tests, usually a more critical factor than performance measurements. Though using a multi-pole filter may remove high-frequency noise and improve THD+N type measurements (when they are made with wide-bandwidth measuring equipment), these same filters degrade frequency response. The TA2024C Evaluation Board uses the Test/Application Circuit in this data sheet, which has a simple two-pole output filter and excellent performance in listening tests. Measurements in this data sheet were taken using this same circuit with a limited bandwidth setting in the measurement instrument.
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Tri path Technol og y, I nc. - Techni cal I nformation
PACKAGE INFORMATION
The package for the TA2024C is a 36-Lead Power Small Outline Package (PSOP), similar to JEDEC outline MO-166, variation AE. Tripath currently has two suppliers for this package. We recommend that the exposed copper heatslug width for the PCB design be at least 7.3mm wide to accommodate the heatslug width variation for each package. Package dimensions are based on millimeters. Measurements in inches are provided as reference only.
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TA2024C -KL/1.0/01.06
Tri path Technol og y, I nc. - Techni cal I nformation
Outline and mechanical data for PSOP36
DIM A A1 A2 A3 D D1 D2 D3 E
MIN -
MAX 3.600
DIM E1
MIN
MAX 11.00 BSC
0.100 3.000 3.300 0.025 0.152 15.90 BSC 9.000 13.000 1.100 1.000 14.200 BSC
E2 2.900 E3 6.300 7.300 E4 2.700 2.900 E5 1.000 L 0.800 1.100 L1 1.60 REF L2 0.350 BSC All DIM measured in mm
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Tri path Technol og y, I nc. - Techni cal I nformation
PRELIMINARY INFORMATION - The above specification is for a device that is currently in development. All specifications and device descriptions are subject to change based on product analysis and characterization. Please contact Tripath Technology for additional information not included or covered in this preliminary document.
Tripath Technology Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Tripath does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. Tripath and Digital Power Processing are trademarks of Tripath Technology Inc. Other trademarks referenced in this document are owned by their respective companies. TRIPATH'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF THE PRESIDENT OF TRIPATH TECHNOLOGY INC. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in this labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Contact Information
TRIPATH TECHNOLOGY, INC
2560 Orchard Parkway, San Jose, CA 95131 408.750.3000 - P 408.750.3001 - F For more Sales Information, please visit us @ www.tripath.com/cont_s.htm For more Technical Information, please visit us @ www.tripath.com/data.htm
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